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CS7615
CCD Imager Analog Processor
Features Description
The CS7615 is a low-power Analog front-end processor for standard four-color interline transfer CCD imagers. The architecture includes a correlated double sampler, AGC amplifier, black-level clamp, 10-Bit A/D converter, and a complete multi-sync CCD timing generator. The analog CCD imager output can be directly connected to the CS7615 input, which does not require an external buffer amplifier. The pixel data is double sampled for improved noise performance, and gain adjusted prior to being digitized by the A/D converter. Feedback from the A/D converter holds the image black level at code-16 (assumes 8-bit data path), addressing ITU-601 compliance issues. The multi-sync CCD timing generator is programmed via the I2C bus, and can be used with a wide range of interline transfer CCD imagers up to 1000 pixels wide. The CS7615 supports full ITU-601 compliance for images up to 720 pixels wide, and is compatible with both NTSC and PAL timing. The CS7615 is designed to be used along with either the CS7665 or CS7666 Digital Color-Space Processor for CCD Cameras, which generates a 4:2:2 component digital video output. ORDERING INFORMATION CS7615-KQ 0 to +70 C (10 mm x 10 mm x 1.6 mm) 44-pin TQFP
l 10-Bit A/D Converter l Multi-Sync CCD Timing Generator,
handles imagers up to 1000 pixels wide l Integrated Correlated Double Sampler l 38 dB Automatic Analog Gain Control l Up to 90 dB Total Gain Adjust Range l Closed-Loop "Fuzzy" AGC/Exposure l Code 16 Black Level Clamp l I2C Control Bus l 4-Phase Vertical CCD Timing Signals l No CCD Buffer Amplifier Required l Master Clock or Crystal Controlled
CCD Output
CDS/AGC
A/D Converter Black Level
Output Formatter
Data Out Clocks Out
AGC Controller Timing Generator Master Clock PLL
Register Block
I2C
I2C Bus
CCD Timing Signals This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved)
Preliminary Product Information
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
JUL `98 DS231PP6 1
CS7615
TABLE OF CONTENTS
ANALOG CHARACTERISTICS: ........................................................................... 3 DIGITAL CHARACTERISTICS: ............................................................................ 3 POWER CONSUMPTION: .................................................................................... 3 CONTROL PORT CHARACTERISTICS: .............................................................. 4 SWITCHING CHARACTERISTICS: ...................................................................... 5 RECOMMENDED OPERATING CHARACTERISTICS: ....................................... 5 ABSOLUTE MAXIMUM RATINGS: ....................................................................... 5 GENERAL DESCRIPTION .................................................................................. 6 Overview ..................................................................................................... 6 Interfacing the CS7615 with CS7665 or CS7666 ....................................... 6 Operation .................................................................................................... 6 CCD Timing Generator ............................................................................... 8 Vertical Timing Specifications ..................................................................... 8 Horizontal Timing Specifications ................................................................. 8 Description of Operation ............................................................................. 9 Automatic Gain Control ............................................................................... 9 Correlated Double Sampling (CDS) .......................................................... 11 Analog to Digital Converter ....................................................................... 15 Black Level Adjust to Code 16 (10-bit Code 64) ....................................... 15 Formatter .................................................................................................. 15 SERIAL CONTROL BUS ................................................................................... 16 Station Address ........................................................................................ 16 Write Operations ................................................................................ 16 Address Set Operation ....................................................................... 16 Read Operations ................................................................................ 16 REGISTER DESCRIPTIONS ............................................................................. 17 PIN DESCRIPTIONS ......................................................................................... 30 PACKAGE DIMENSIONS .................................................................................. 34
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ANALOG CHARACTERISTICS:
Parameter (TA=25 C; VAA=VDD=5V; Output Load=30pF ) Symbol INL DNL CIN GMAX GMIN G Min Typ 1 0.75 10 20 0 78.4 Max 117.6 Units LSB LSB pF dB dB mdB
Dynamic Performance Integral Non-Linearity Differential Non-Linearity Analog Input Analog Input Capacitance Automatic Gain Control Maximum Gain Minimum Gain Gain Increment
DIGITAL CHARACTERISTICS: (TA=25 C; VAA=VDD=5V; Output Load=30pF )
Parameter Symbol VIH VIL IIN IOH IOL IOZ Min VDD-0.8 Typ Max 0.8 10 1 1 10 Units V V mA mA mA A
Logic Inputs High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Logic Outputs High-Level Output Source Current @ VOH = VDD-0.4V Low-Level Output Sink Current @ VOL = 0.4V 3-State Leakage Current
POWER CONSUMPTION: (TA=25 C; VAA=VDD=5V; Output Load=30pF )
Parameter Power Dissipation Analog Power Supply Current DIgital Power Supply Current Normal Mode Low-Power Mode Normal Mode Low-Power Mode Symbol PD IAN IALP IDN IDLP Min Typ 650 99 63 55 22 Max Units mW mA mA mA mA
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CONTROL PORT CHARACTERISTICS: (TA=25 C; VAA=VDD=5V; Output Load=30pF )
Parameter SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Pulse Width Setup TIme for Repeat Start Condition SDAIN Hold Time from SCL Falling SDAIN Setup Time from SCL Rising SDAIN and SCL Rise Time SDAIN and SCL Fall Time Setup Time for Stop Condition High Low Symbol fSCL tbuf thdst thigh tlow tsust thdd tsud tr tf tsusp Min 4.7 4.0 4.0 4.7 4.7 0 0.25 4.0 Typ Max 100 1.0 0.3 Units kHz s s s s s s s s s s
Stop SD A t SCL
Start
Repeated Start
Stop
buf
t
hdst
t high
t hdst
tf
t
susp
t
low
t
hdd
Figure 1. I2C
t
sud
t
sust
t
r
Timing Diagram
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SWITCHING CHARACTERISTICS: (TA=25 C; VSS=VDD=5V; Output Load=30pF )
Parameter Crystal Frequency Range Crystal Oscillator Duty Cycle CLKO Frequency CLK2XO Frequency CLKO duty cycle CLK2XO duty cycle CLK2XO falling edge to CLKO falling edge FR Clock (CCD reset gate clock) Duty Cycle H1 Clock Duty Cycle H2 Clock Duty Cycle 4 25 50 50 fpix fdat Symbol fCRY Min 6.75 40 6.75 13.5 50 50 8 Typ Max 27 60 13.5 27 Units MHz % MHz MHz % % ns % % %
RECOMMENDED OPERATING CHARACTERISTICS:
V AC V AIN V DC Feedthrough Level
GND
Figure 2. Analog Input Parameter Power Supply Voltage GNDA to GNDD Voltage Differential Crystal Frequency Range Analog Input AC Range (Figure 2) Analog Input DC Offset (Figure 2) Analog Input Voltage (Figure 2) VAC VDC AIN 0 6.75 0 12 18 Symbol VAA, VDD Min 4.5 Typ 5.0 Max 5.5 10 27 1.65 Units V mV MHz V V V
ABSOLUTE MAXIMUM RATINGS:
Parameter Power Supply Voltage Digital Input Voltage Analog Input Voltage - AIN only Input Current Ambient Temperature Range Lead Solder Temperature (10sec duration) Storage Temperature Range -65 Specifications are subject to change without notice. (except supply pins) -0 AIN Symbol VAA, VDD Min -0.3 GNDD-0.3 GNDA-(0.3) Max 7.0 (VDD)+0.3 20 10 +70 +260 +150 Units V V V mA C C C
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CS7615
GENERAL DESCRIPTION Overview
The CS7615 performs the analog functions in a four chip digital CCD Camera. The four main chips include the CCD imager, the CS7615 CCD digitizer, the CS7665 or CS7666 color space processor, and a vertical drive interface-chip for the CCD imager. Several CCD imagers (and their associated vertical drivers) can be used with the CS7615 digitizer and the CS7665 or CS7666 processor to form a simple and cost-effective YCrCb output format digital camera. The block diagram in Figure 3 illustrates the system interconnect.
4:2:2, H.656 VIDEO CS7615
CCD CDS/ADC
Interfacing the CS7615 with CS7665 or CS7666
The CS7666 is a direct replacement for the CS7665. No board or software changes are needed for existing designs. However, slight changes to existing hardware and software are necessary to take advantage of the CS7666. See Figure 4 and 5 and the CS7666 data sheet for more details.
Operation
The CS7615 digitizer is designed to provide all necessary analog functions and conversion to digital data of a standard CCD imager output signal as well as provide all the timing and control signals for the CCD imager. The architecture includes a correlated double sampler, variable gain amplifier with an integrated AGC loop, black level clamp, 10-bit A/D converter, output formatter, and a complete multi-sync CCD timing generator. The output of the A/D converter ranges from code 004h to code 3FBh and the formatter adds special end-ofactive-video (EAV) and start-of-active-video (SAV) codes to each line, making the output of the CS7615 similar to the description in the ITU-656 recommendation.
CS7665 or CS7666
IMAGE PROCESSOR CS4952 or CS4954
7 512x480
VERTICAL DRIVE 9
TIMING
2 IC
2 IC
2
2 I C BUS
+8 V TO +12 V
DC-DC CONVERTER
+5 V
Figure 3. Typical 4-Chip Digital CCD Camera
32 XTAL 33
CS7615
39 4
CLK2x0 CLOCK CLK0 10-BIT DATA
56 55
CS7665
Figure 4. CS7615/CS7665 Interface
NC 33 CS7615 39 4 32 XTALIN 10-BIT DATA CCLOKG NC CLK0 CS7666 56 55 CLKIN 52 XTAL
Figure 5. CS7615/CS7666 Interface
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The EAV/SAV code definitions are consistent with an 8-bit data path. As per the ITU-656 recommendation, the LSB's of the CS7615 are fractional bits which are not used when delivering 8-bit output data. In 10-bit mode, all ten digital outputs can be connected directly to the CS7665. The output data format from the CS7615 formatter is shown in Figure 6. The CS7615 also outputs two clocks, one at the pixel rate and the other at 2x the
HREF Blanking period Active video
output pixel data rate (see pin description for CLK2XO). The output of the formatter is available at the pins DO[0..9] and it transitions at the falling edge of the pixel rate clock CLKO. Figure 7 shows the basic output timing diagram. The falling edges of CLKO lag the falling edges of CLK2XO by 4 to 8 ns and both clocks have approximately 50% duty cycles.
4T
Nb T
4T
AV*T T = output pixel period
EAV code (10 bits) Smpl. 0 1 2 3 Word 3FFh 000h 000h Binary 1fv1P3P2P1P000
During active video, samples of mosaic data; during vertical blanking, 040h.
At reset or power down, 040h.
SAV code (10 bits) Smpl. 0 Word 3FFh 000h 000h Binary 1fv0P3P2P1P000
Blank code (10 bits) Smpl. 4 Word 040h repeat above word
1 2 3
f = field bit; 0 (odd field), 1 (even field) v = vertical blanking bit; 0 (active video lines), 1(vertical blanking) P3P2P1P0 = error protection bits (as per ITU-656).
Figure 6. CS7615 Output Data Format
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CLK2XO
CLKO
DO[0..9]
Figure 7. CS7615 Output Data and Clocks
CCD Timing Generator
The CCD timing and control signal outputs are dictated by the programmable register settings. This allows for compatibility with a variety of CCDs. The HSYNC signal is also output for use in a genlock configuration. The open-drain HCLK can be used to clock dc-dc voltage converters which are typically used to generate the CCD imager bias voltages. The following description explains the various output signals provided to the vertical driver and CCD as well as the programmable parameters that may be set to control these signals. HREF* - horizontal reference signal. It stays high during the active video portion of the line. HENB* - Horizontal shift register clock enable signal. Enables H1 and H2 out of analog timing. CLAMP* - Black clamp signal provided to the ADC. V1X, V2X, V3X, V4X - Vertical register shift clock. Used both during vertical transfer and charge read out. VH1X, VH3X - CCD charge read out pulse. HCLK - Signal used by the dc - dc converter. In the normal mode, it is the same as HREF; In fast mode, it operates at about 16x of the horizontal line frequency and is reset at the begin8
ning of HREF. HSYNC - Horizontal sync signal. OFDX - Overflow drain control clock. This signal sets the electronic shutter speed. VRST - Vertical field reset signal. VREF* - Vertical reference signal. It is high during the active video lines. *Internal signal on the CS7615 - not a chip output.
Vertical Timing Specifications
The CCD array is read out alternately as odd and even fields with interlaced horizontal lines. Thus each field has half the total number of horizontal rows. Table 1 specifies the programmable vertical timings which are defined in Figure 8. The timings vary based on odd or even field, 525 or 625 line CCD, and the manufacturer.
Horizontal Timing Specifications
Each horizontal row of the CCD is divided into several regions corresponding to the type of pixels present. Different CCDs have different numbers of pixels in each region and the timing signals must take this into account. The different pixel types include optical black pixels (front and rear), dummy pixels, active video pixels, and blank video. The horizontal timing for the CCD is based on maintaining a fixed 63.5 s horizontal line time.
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Figure 10 shows the timings for the V1X through V4X signals. The specified waveforms repeat on every horizontal line except during the charge transfer line. During this line the CCD charge is read out and the timing is different as shown in Figure 11. In addition signals VH1X and VH3X are also required during charge read out as shown in Figure 12. The overflow drain control signal is shown in Figure 13. The OFDX signal is used to control the electronic shutter timing of the CCD. Shutter timing for various settings of the shutter control is described in the register section of this document.
Symbol VLO VLE VBO XSO VBE XSE
Description # of lines in odd field # of lines in even field End of VREF line # Charge transfer line # End of VREF line # Charge transfer line #
Register 33h, 39h 34h, 39h 36h, 39h 38h, 39h 35h, 39h 37h, 39h
Table 1. CCD vertical timing specifications
Table 2 specifies all of the programmable timing parameters related to horizontal timing signals. These parameters are defined in Figure 9. Figure 9 shows the timings for HREF, HSYNC, CLAMP, and HENB. Their relationship to different kinds of pixels on each horizontal row output from the CCD is also shown. The waveforms for these signals are repeated on every line. The horizontal shift register clocks, H1 and H2, operate at the CLKO frequency and are active throughout the horizontal line period except when HENB is high.
Description of Operation
The internal operation of the CS7615 can be separated into several distinct blocks. The following section provides an overview of how these blocks operate and interact.
Automatic Gain Control
The pixel data entering the CS7615 from the CCD is scaled as determined by the automatic gain control loop. By properly applying gain to the signal, the full range of the A/D converter is used. The in-
VLO VBO: end of VREF VREF* 1
VLE VBE: end of VREF
XSO: charge transfer line
XSE: charge transfer line
HREF Not to scale FLD
Figure 8. Vertical Timing Signals -Internal to CS7615
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CS7615
Hlen HBPD HREF Active Video
0 Hsynf Hsnyr
HSYNC BC
CLAMP Hend Hstart HENB
CCD OUTPUT
Optical black pixels
Inactive video
Active video
Figure 9. Timing Diagram for Href, HSYNC, Clamp, and Henb
ternal analog gain range is 38 dB in steps of 0.078 dB ideal. Adjustments made in these small steps should cause no noticeable brightness change in the image from frame to frame. In addition to the internal analog gain, the control loop will vary the shutter speed through the OFDX output from 0 to 54 dB as it deems necessary. The AGC algorithm uses a luma or mosaic histogramming technique in which the brightness of each pixel is binned into one of seven bins. The
10
number of pixels in a bin will produce an error signal that is then used to update the gain. The following parameters control the loop dynamics and are programmable to meet the needs of the user. PAL bit: Selects a PAL or NTSC camera system. AGC Window: Adjusts what portion of the frame is used for the AGC algorithm. Luma/Mosaic: Selects whether luma or mosaic data are used in the histogramming.
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HREF
V1f V1r
V1X
V2f V2r
V2X
V3X
V3f V3r
V4X
V4f V4r
Figure 10. Vertical Shift Register Signal Timings
Flickerless Mode: Restricts the shutter speed to only flickerless values for the given system and environment. If the scene is too bright, the AGC loop will select exposure settings shorter than the flickerless modes. PAL Environment: Selects PAL or NTSC environment. Target Value: Adjusts the brightness threshold. A lower target results in the loop settling to a lower gain. Max Gain: Sets a maximum gain value that will not be exceeded even if the target brightness has not been met. Slew: Controls the rate of decay of the gain as
the AGC loop slews because of light intensity variation. Speed: Controls the overall loop gain and thus speed of gain correction. Min Gain: Sets the minimum on-chip gain allowed. This value should be used if the saturation voltage is less than 1.6V.
Correlated Double Sampling (CDS)
Correlated Double Sampling, as applied to CCDbased imaging systems, is a method used to remove low-frequency noise from the output of a CCD imager leaving only the signal of interest. The CDS is applied prior to amplification by the VGA.
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CS7615
Note: line #s shown here are for 525 line systems
HREF
LINE #17
LINE #18
V1X ODD FIELD V2of V2or V2X
V3X V3of V4X
V3or
HREF
LINE #279
LINE #280
(no pulse on V1X) EVEN FIELD V1X V2er V2X V3ef V3X V3er V2ef
V4ef V4X V4er
Figure 11. Vertical Shift Register Signal Timings for Charge Read Out Phase
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LINE #17 and #279 HREF
Note: Line #s shown are for 525 line system.
VH1X
VH1r VH1f
VH3X
VH3r VH3f
Figure 12. Charge Read Out Signal Timing
19 H VREF
262 H or 263 H
OFDX
HREF
Horizontal line count = Shutter control register value
Notes: OFDX remains high when shutter is set to 00h. Line #s shown are for 525 line system. OFDW
OFDX
Figure 13. Electronic Shutter Control Signal Timing
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CS7615
Symbol HBPD Hlen Hsynr Hsynf BC Hend Hstart V1r V1f V2r V2f V3f V3r V4f V4r V2or V2of V3of V3or V2er V2ef V3ef V3er V4ef V4er VH1f VH1r VH3f VH3r OFDW Description Horizontal blanking period Total number of horizontal pixels
HREF to HSYNC leading edge HREF to HSYNC trailing edge HREF to CLAMP leading edge
Register 40h 41h, 42h 43h 44h 45h 46h 47h 48h 47h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h, 52h 51h, 52h 53h, 55h 54h 56h, 58h 57h 59h, 5Bh 5Ah 5Ch, 5Eh 5Dh 5Fh, 61h 60h, 61h 62h, 64h 63h, 64h 65h
(clamp trailing edge at Hend)
HREF to HENB leading edge
Hz. clock disable period V1 clock leading edge V1 clock trailing edge V2 clock leading edge V2 clock trailing edge V3 clock leading edge V3 clock trailing edge V4 clock leading edge V4 clock trailing edge V2odd clock leading edge V2odd clock trailing edge V3odd clock leading edge V3odd clock trailing edge V2even clock leading edge V2even clock trailing edge V3even clock leading edge V3even clock trailing edge V4even clock leading edge V4even clock trailing edge Charge read clock leading edge Charge read clock trailing edge Charge rd clock leading edge Charge rd clock trailing edge OFDW pulse width Table 2. Horizontal timing specifications
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Analog to Digital Converter
After the pixel data is double sampled and the appropriate gain has been applied, it is digitized by the internal 10-bit A/D converter. These resulting mosaic data are input to the formatter which formats the data before sending it to the chip output. The output of the A/D converter is also used by the internal AGC loop in determining the proper gain setting, and by the black level adjust when reading the black pixels. is programmable by the user through the I2C interface.
Formatter
The formatter adds the necessary EAV/SAV timing codes to the output data in accordance with the ITU-656 recommendation.
Black Level Adjust to Code 16 (10-bit Code 64)
The output data are adjusted to hold the image black level at the 8-bit code of 16, in compliance to the ITU-601 recommendation. During the blanking periods, the black level adjustment is updated when over black pixels. The number of black pixels used
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CS7615
SERIAL CONTROL BUS
The serial control bus protocol is an 8-bit protocol controlled receiver. To the receiver, the control bus looks like an 8-bit bi-directional channel down which short packets are sent or received. Each source device appears to the receiver as a set of 8bit registers, which are addressable to a device through a station address. Packets are used to write and read the contents of these device registers. There are three packet formats: WRITE format, ADDRESS SET format, and READ format. Each packet is addressed to a device by its station address. The LSB of the station address is the data direction bit. This bit is set LOW in the WRITE and ADDRESS SET packets, and it is set HIGH for READ packets. The receiver can read and write to non-existent registers within the selected device. WRITE operations will have no effect; READ operations will return a value of 00h. third byte is the register data (0..255). No extra bytes should be sent.
Byte Sequence First Byte Second Byte Third Byte WRITE Format Packet Detail Station Address with LSB Set LOW Device Register Address (0..255) Register Data (0..255)
Table 3. WRITE Format Packet
Address Set Operation
The ADDRESS SET format consists of a two-byte packet which sets the address of a subsequent READ operation. The first byte of the station Address with the LSB (data direction bit) set LOW to indicate a write operation. The second byte is the register address (0..255). The ADDRESS SET format is the same as the WRITE format, without the register data.
Byte Sequence First Byte Second Byte ADDRESS SET format Packet Details Station Address with LSB Set LOW Device Register Address (0..255)
Station Address
The CS7615 rev A default station address is A8h for writes and A9h for reads. Subsequent versions of the CS7615, starting with rev B, will use a default station address of 68h for writes and 69h for reads. The station address can be changed by writing a new base station address to internal I2C register FEh. Note that the station address register describes only the 7 MSBs of the CS7615 station address. The base write address will need to be right shifted by one place before being written into the FEh register.
Table 4. ADDRESS SET Format Packet Operation
Read Operations
The READ operation consist of two or more bytes. The first byte is the station address with the LSB (data direction bit) set HIGH indicating a read operation. The addressed device then sends one or more bytes back from the register last addressed by the previous WRITE operation, or ADDRESS SET operation.
Byte Sequence First Byte READ Format Packet Details Station Address with LSB set HIGH; Source Device then Returns One Byte of Register Data (0..255) Returned data from CS7615
Write Operations
The WRITE format consists of a three-byte packet. The first byte is the station address with the data direction bit set LOW to indicate a write. The second byte is the device register address (0..255). The
Second Byte
Table 5. READ Format Packet.
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REGISTER DESCRIPTIONS
Software Reset Register (00h)
7 res r 6 res r 5 res r 4 SR4 w 3 res r 2 res r 1 res r 0 res r
SR4
Setting bit SR4 to logic high will initiate a CS7615 software reset. Software reset resets all the digital blocks except for I2C and the ADC calibration logic. The clocks remain running. This reset bit automatically clears.
Low Power Register (20h)
7 res r 6 res r 5 res r 4 PD4 r/w 3 res r 2 res r 1 res r 0 res r
PD4
Setting bit PD4 to logic high will place the CS7615 chip in a low power mode. The I2C interface and clock generation circuitry will remain powered up.
Operational control #1 Register (24h)
7 PAL r/w 6 AGCW1 r/w 5 AGCW2 r/w 4 AGCDIS r/w 3 AGCCALG r/w 2 CCDTYP r/w 1 FLCKLS r/w 0 PALENV r/w
PAL AGCW
Logic high indicates a PAL standard camera system, logic low indicates NTSC. Default = 0. Used to window the portion of the frame to use for AGC. Default = 00. 00 = use entire frame 01 = use center 1/4 area of frame 10 = use center 1/16 area of frame 11 = reserved Logic high disables CS7615's automatic gain control circuitry. User may manually control gain through the gain register 25h/26h. Default = 0. Controls data used in CS7615's AGC loop. Logic high indicates mosaic data, logic low indicates luma data. Default = 0. Logic high signifies that a Type B CCD is being used, logic low signifies a Type A CCD. Default = 0. Logic high restricts shutter to flickerless settings. Default = 0. Logic high when the camera system is being used in a PAL environment, logic low in an NTSC environment. Default = 0. Read/Write Read Write Reserved
AGCDI AGCALG CCDTYP FLCKLS PALENV R/W R W RES
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Gain Registers (25-26h)
25h:
7 AGC10 r/w 6 AGC9 r/w 5 AGC8 r/w 4 AGC7 r/w 3 AGC6 r/w 2 AGC5 r/w 1 AGC4 r/w 0 AGC3 r/w
26h:
7 res r 6 res r 5 res r 4 res r 3 res r 2 AGC2 r/w 1 AGC1 r/w 0 AGC0 r/w
AGC(10:0)
Gain control word for the automatic gain control. This 11 bit word is a 2's compliment number which has a minimum value of -784 (decimal) (Reg 26h = 04h; Reg 25h = 5F0h) for PAL or 765d for NTSC (Reg 26h = 05h; Reg 25h = 03) and a maximum value of 484d (Reg 26h = 01h; Reg 25h = E4h). The gain range is -54 dB to 38 dB in steps of 0.078 dB ideal, 0.12 dB max step is guaranteed only for chip GAIN. Default is 000h.
AGC Error Statistic Register (27h):
7 agcer7 r 6 agcer6 r 5 agcer5 r 4 agcer4 r 3 agcer3 r 2 agcer2 r 1 agcer1 r 0 agcer0 r
AGCER
The 8 MSBs of the gain error statistic calculated as part of the AGC loop.
AGC Count Statistic Register (28h)
7 res r 6 agcct6 r 5 agcct5 r 4 agcct4 r 3 agcct3 r 2 agcct2 r 1 agct1 r 0 agcct0 r
AGCCT
The output of the 1-of-7 block which denotes the bin where the AGC target was met.
AGC Target Value Register (29h)
7 res r 6 res r 5 res r 4 res r 3 res r 2 agctg2 r/w 1 agctg1 r/w 0 agctg0 r/w
AGCTG
The target value used in the AGC loop. It denotes the number of pixels that must be exceeded for an intensity bin to give an output of `1'. Default is 0h. 000=64 100=1024 001=128 101=2048 010=256 110=4096 011=512 111=8192
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AGC Maximum Gain Register (2Ah)
7 mgn7 r/w 6 mgn6 r/w 5 mgn5 r/w 4 mgn4 r/w 3 mgn3 r/w 2 mgn2 r/w 1 mgn1 r/w 0 mgn0 r/w
MGN
Sets the maximum gain allowable if the user chooses to limit the chip gain beyond a certain value. The range is 0-242, with the actual max gain word being twice this value. Default is F2h.
AGC Slew and Speed Register (2Bh)
7 res r 6 res r 5 res r 4 res r 3 slew1 r/w 2 slew0 r/w 1 spd1 r/w 0 spd0 r/w
SLEW
Sets the rate of decay of gain when the gain target is exceeded in the maximum intensity bin. Default is 0h. 00 = -8 10 = -32 01 = -16 11 = -64 Varies the AGC loop gain. The error signal used for correction is multiplied by the speed number before being added to the accumulator. Default is 0h. 00 = 1x 10 = 4x 01 = 2x 11 = 8x
SPD
AGC Minimum Gain Register (2Ch)
7 mng7 r/w 6 mng6 r/w 5 mng5 r/w 4 mng4 r/w 3 mng3 r/w 2 mng2 r/w 1 mng1 r/w 0 mng0 r/w
MNGN
Sets the minimum gain allowable if the user chooses to limit the chip gain from a certain value. Default is 00h.
CCD Signal Alignment Register (2Dh)
7 HR1 r/w 6 HR0 r/w 5 HF1 r/w 4 HF0 r/w 3 FRR1 r/w 2 FRR0 r/w 1 FRF1 r/w 0 FRF0 r/w
These signals adjust the edges of H1 or FR with respect to the internal sampling clock. HR HF FRR FRF Adjusts the location of the rising edge of H1. Adjusts the location of the falling edge of H1. Adjusts the location of the rising edge of FR. Adjusts the location of the falling edge of FR.
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CS7615
VRST Registers (2Eh, 2Fh)
2Eh:
7 VRSTN8 r/w 6 VRSTN7 r/w 5 VRSTN6 r/w 4 VRSTN5 r/w 3 VRSTN4 r/w 2 VRSTN3 r/w 1 VRSTN2 r/w 0 VRSTN1 r/w
2Fh:
7 res r 6 res r 5 res r 4 res r 3 res r 2 VRSTDY r/w 1 VRSTFLD r/w 0 VRSTN0 r/w
These parameters are needed only when the VRST input is used. VRSTN VRSTDY VRSTFLD The line number gets reset to this value on a negative edge of VRST. Default is 004h. Logic high denotes VRST will be delayed with respect to the line position. Default = 0 (no delay). Logic high denotes the field is reset to even on a negative edge of VRST, logic low denotes the field is reset to odd. Default = 0.
Maximum Shutter Exposure Register (30h)
7 MSXH7 r/w 6 MSXH6 r/w 5 MSXH5 r/w 4 MSXH4 r/w 3 MSXH3 r/w 2 MSXH2 r/w 1 MSXH1 r/w 0 MSXH0 r/w
MXSH
If the user chooses to limit the exposure time, the max shutter gain is set to this value. 00h=full exposure, BFh=min exposure for NTSC, C4h= min exposure for PAL.
Operational Control #2 Register (31h)
7 res r 6 res r 5 res r 4 res r 3 BLKDIS r/w 2 ADCAL1 r/w 1 ADCAL2 r/w 0 CNVFST r/w
BLKDIS ADCAL1 ADCAL2 CNVFST
Logic high disables the black level loop. Black level remains at the current value. Default =0. Analog-to-digital converter option. When written to a logic high, calibration is immediately entered. This bit goes back low when calibration is complete. Analog-to-digital converter option. Logic high results in calibration being done after every frame, logic low results in calibration only on power up. Default = 0. Logic high sets the frequency of HCLK to 16xthe line frequency, logic low sets HCLK to 1xthe line frequency. Default = 0.
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Timing Control- Line Number Registers (33h-39h)
33h:
7 VLO8 r/w 6 VLO7 r/w 5 VLO6 r/w 4 VLO5 r/w 3 VLO4 r/w 2 VLO3 r/w 1 VLO2 r/w 0 VLO1 r/w
34h:
7 VLE8 r/w 6 VLE7 r/w 5 VLE6 r/w 4 VLE5 r/w 3 VLE4 r/w 2 VLE3 r/w 1 VLE2 r/w 0 VLE1 r/w
35h:
7 VBE8 r/w 6 VBE7 r/w 5 VBE6 r/w 4 VBE5 r/w 3 VBE4 r/w 2 VBE3 r/w 1 VBE2 r/w 0 VBE1 r/w
36h:
7 VBO8 r/w 6 VBO7 r/w 5 VBO6 r/w 4 VBO5 r/w 3 VBO4 r/w 2 VBO3 r/w 1 VBO2 r/w 0 VBO1 r/w
37h:
7 XSE8 r/w 6 XSE7 r/w 5 XSE6 r/w 4 XSE5 r/w 3 XSE4 r/w 2 XSE3 r/w 1 XSE2 r/w 0 XSE1 r/w
38h:
7 XSO8 r/w 6 XSO7 r/w 5 XSO6 r/w 4 XSO5 r/w 3 XSO4 r/w 2 XSO3 r/w 1 XSO2 r/w 0 XSO1 r/w
39h:
7 res r 6 res r 5 VLO0 r/w 4 VLE0 r/w 3 VBE0 r/w 2 VBO0 r/w 1 XSE0 r/w 0 XSO0 r/w
VLO VLE VBE VBO XSE XSO DS231PP6
The number of lines in an odd field. Default is 106h. The number of lines in an even field. Default is 107h. Line number for end of VREF for even field. Default is 013h. Line number for end of VREF for odd field. Default is 012h. Line number for charge transfer for even field. Default is 011h. Line number for charge transfer for odd field. Default is 010h. 21
CS7615
Timing Control-Horizontal Blank Pd Register (40h)
7 HBPD7 r/w 6 HBPD6 r/w 5 HBPD5 r/w 4 HBPD4 r/w 3 HBPD3 r/w 2 HBPD2 r/w 1 HBPD1 r/w 0 HBPD0 r/w
HBPD
Number of pixel clocks in the horizontal blank period. Default is 70h.
Timing Control- Line Length Register (41h-42h)
41h:
7 HLEN9 r/w 6 HLEN8 r/w 5 HLEN7 r/w 4 HLEN6 r/w 3 HLEN5 r/w 2 HLEN4 r/w 1 HLEN3 r/w 0 HLEN2 r/w
42h:
7 res r 6 res r 5 res r 4 res r 3 res r 2 res r 1 HLEN1 r/w 0 HLEN0 r/w
HLEN
Total number of pixels in line length. Default is 270h.
Timing Control- HSYNC Registers (43h-44h)
43h:
7 HSYNR7 r/w 6 HSYNR6 r/w 5 HSYNR5 r/w 4 HSYNR4 r/w 3 HSYNR3 r/w 2 HSYNR2 r/w 1 HSYNR1 r/w 0 HSYNR0 r/w
44h:
7 HSYNF7 r/w 6 HSYNF6 r/w 5 HSYNF5 r/w 4 HSYNF4 r/w 3 HSYNF3 r/w 2 HSYNF2 r/w 1 HSYNF1 r/w 0 HSYNF0 r/w
HSYNR HSYNF
Number of pixels from HREF to leading edge of HSYNC. Default is 14h. Number of pixels from HREF to trailing edge of HSYNC. Default is 44h.
Timing Control - Black Clamp Register (45h)
7 BC7 r/w 6 BC6 r/w 5 BC5 r/w 4 BC4 r/w 3 BC3 r/w 2 BC2 r/w 1 BC1 r/w 0 BC0 r/w
BC
Number of pixels from HREF to leading edge of black clamp. Default is 08h. Black clamp falls on leading edge of HENB.
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Timing Control - HENB Registers (46h-47h)
46h:
7 HEND7 r/w 6 HEND6 r/w 5 HEND5 r/w 4 HEND4 r/w 3 HEND3 r/w 2 HEND2 r/w 1 HEND1 r/w 0 HEND0 r/w
47h:
7 HSTART7 r/w 6 HSTART6 r/w 5 HSTART5 r/w 4 HSTART4 r/w 3 HSTART3 r/w 2 HSTART2 r/w 1 HSTART1 r/w 0 HSTART0 r/w
HEND HSTART
Number of pixels from HREF to leading edge of HENB. Default is 1Ch. Number of pixels from HREF to trailing edge of HENB. Default is 68h.
Timing Control - V1X Registers (48h-49h)
48h:
7 V1R7 r/w 6 V1R6 r/w 5 V1R5 r/w 4 V1R4 r/w 3 V1R3 r/w 2 V1R2 r/w 1 V1R1 r/w 0 V1R0 r/w
49h:
7 V1F7 r/w 6 V1F6 r/w 5 V1F5 r/w 4 V1F4 r/w 3 V1F3 r/w 2 V1F2 r/w 1 V1F1 r/w 0 V1F0 r/w
V1X is a vertical register shift clock. V1R V1F Number of pixels from HREF to leading edge of V1X. Default is 22h. Number of pixels from HREF to trailing edge of V1X. Default is 36h.
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Timing Control - V2X Registers (4Ah-4Bh)
4Ah:
7 V2R7 r/w 6 V2R6 r/w 5 V2R5 r/w 4 V2R4 r/w 3 V2R3 r/w 2 V2R2 r/w 1 V2R1 r/w 0 V2R0 r/w
4Bh:
7 V2F7 r/w 6 V2F6 r/w 5 V2F5 r/w 4 V2F4 r/w 3 V2F3 r/w 2 V2F2 r/w 1 V2F1 r/w 0 V2F0 r/w
V2X is a vertical register shift clock. V2R V2F Number of pixels from HREF to leading edge of V2X. Default is 2Ch. Number of pixels from HREF to trailing edge of V2X. Default is 40h.
Timing Control - V3X Registers (4Ch-4Dh)
4Ch:
7 V3F7 r/w 6 V3F6 r/w 5 V3F5 r/w 4 V3F4 r/w 3 V3F3 r/w 2 V3F2 r/w 1 V3F1 r/w 0 V3F0 r/w
4Dh:
7 V3R7 r/w 6 V3R6 r/w 5 V3R5 r/w 4 V3R4 r/w 3 V3R3 r/w 2 V3R2 r/w 1 V3R1 r/w 0 V3R0 r/w
V3X is a vertical register shift clock. V3F V3R Number of pixels from HREF to leading edge of V3X. Default is 1Dh. Number of pixels from HREF to trailing edge of V3X. Default is 3Bh.
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Timing Control - V4X Registers (4Eh-4Fh):
4Eh:
7 V4F7 r/w 6 V4F6 r/w 5 V4F5 r/w 4 V4F4 r/w 3 V4F3 r/w 2 V4F2 r/w 1 V4F1 r/w 0 V4F0 r/w
4Fh:
7 V4R7 r/w 6 V4R6 r/w 5 V4R5 r/w 4 V4R4 r/w 3 V4R3 r/w 2 V4R2 r/w 1 V4R1 r/w 0 V4R0 r/w
V4X is a vertical register shift clock. V4F V4R Number of pixels from HREF to leading edge of V4X. Default is 29h. Number of pixels from HREF to trailing edge of V4X. Default is 45h.
Timing Control - Charge Read Out in Odd Field V2X Registers (50h-52h)
50h:
7 V2OR9 r/w 6 V2OR8 r/w 5 V2OR7 r/w 4 V2OR6 r/w 3 V2OR5 r/w 2 V2OR4 r/w 1 V2OR3 r/w 0 V2OR2 r/w
51h:
7 V2OF9 r/w 6 V2OF8 r/w 5 V2OF7 r/w 4 V2OF6 r/w 3 V2OF5 r/w 2 V2OF4 r/w 1 V2OF3 r/w 0 V2OF2 r/w
52h:
7 res r 6 res r 5 res r 4 res r 3 V2OF1 r/w 2 V2OF0 r/w 1 V2OR1 r/w 0 V2OR0 r/w
Charge readout timing for V2X in an odd field in number of pixels. V2OR V2OF From HREF to leading edge of V2X. Default is 185h. From HREF to trailing edge of V2X. Default is 1E9h.
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Timing Control - Charge Read Out in Odd Field V3X Registers (53h-55h)
53h:
7 V3OF9 r/w 6 V3OF8 r/w 5 V3OF7 r/w 4 V3OF6 r/w 3 V3OF5 r/w 2 V3OF4 r/w 1 V3OF3 r/w 0 V3OF2 r/w
54h:
7 V3OR7 r/w 6 V3OR6 r/w 5 V3OR5 r/w 4 V3OR4 r/w 3 V3OR3 r/w 2 V3OR2 r/w 1 V3OR1 r/w 0 V3OR0 r/w
55h:
7 res r 6 res r 5 res r 4 res r 3 res r 2 res r 1 V3OF1 r/w 0 V3OF0 r/w
Charge readout timing for V3X in an odd field in number of pixels. V3OF V3OR From HREF to leading edge of V3X. Default is 188h. From HREF to trailing edge of V3X. Default is 3Bh.
Timing control - Charge Read Out in Even Field V2X Registers (56h-58h)
56h:
7 V2ER9 r/w 6 V2ER8 r/w 5 V2ER7 r/w 4 V2ER6 r/w 3 V2ER5 r/w 2 V2ER4 r/w 1 V2ER3 r/w 0 V2ER2 r/w
57h:
7 V2EF7 r/w 6 V2EF6 r/w 5 V2EF5 r/w 4 V2EF4 r/w 3 V2EF3 r/w 2 V2EF2 r/w 1 V2EF1 r/w 0 V2EF0 r/w
58h:
7 res r 6 res r 5 res r 4 res r 3 res r 2 res r 1 V2ER1 r/w 0 V2ER0 r/w
Charge readout timing for V2X in an even field in number of pixels. V2ER V2EF From HREF to leading edge of V2X. Default is 185h. From HREF to trailing edge of V2X. Default is 40h.
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Timing Control - Charge Read Out in Even Field V3X Registers (59h-5Bh)
59h:
7 V3EF9 r/w 6 V3EF8 r/w 5 V3EF7 r/w 4 V3EF6 r/w 3 V3EF5 r/w 2 V3EF4 r/w 1 V3EF3 r/w 0 V3EF2 r/w
5Ah:
7 V3ER7 r/w 6 V3ER6 r/w 5 V3ER5 r/w 4 V3ER4 r/w 3 V3ER3 r/w 2 V3ER2 r/w 1 V3ER1 r/w 0 V3ER0 r/w
5Bh:
7 res r 6 res r 5 res r 4 res r 3 res r 2 res r 1 V3EF1 r/w 0 V3EF0 r/w
Charge readout timing for V3X in an even field in number of pixels. V3EF V3ER From HREF to leading edge of V3X. Default is 188h. From HREF to trailing edge of V3X. Default is 3Bh.
Timing Control - Charge Read Out in Even Field V4X Registers (5Ch-5Eh)
5Ch:
7 V4EF9 r/w 6 V4EF8 r/w 5 V4EF7 r/w 4 V4EF6 r/w 3 V4EF5 r/w 2 V4EF4 r/w 1 V4EF3 r/w 0 V4EF2 r/w
5Dh:
7 V4ER7 r/w 6 V4ER6 r/w 5 V4ER5 r/w 4 V4ER4 r/w 3 V4ER3 r/w 2 V4ER2 r/w 1 V4ER1 r/w 0 V4ER0 r/w
5Eh:
7 res r 6 res r 5 res r 4 res r 3 res r 2 res r 1 V4EF1 r/w 0 V4EF0 r/w
Charge readout timing for V4X in an even field in number of pixels. V4EF V4ER From HREF to leading edge of V4X. Default is 1E9h. From HREF to trailing edge of V4X. Default is 45h.
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CS7615
Timing Control - H1X Registers (5Fh-61h)
5Fh:
7 VH1F9 r/w 6 VH1F8 r/w 5 VH1F7 r/w 4 VH1F6 r/w 3 VH1F5 r/w 2 VH1F4 r/w 1 VH1F3 r/w 0 VH1F2 r/w
60h:
7 VH1R9 r/w 6 VH1R8 r/w 5 VH1R7 r/w 4 VH1R6 r/w 3 VH1R5 r/w 2 VH1R4 r/w 1 VH1R3 r/w 0 VH1R2 r/w
61h:
7 res r 6 res r 5 res r 4 res r 3 VH1R1 r/w 2 VH1R0 r/w 1 VH1F1 r/w 0 VH1F0 r/w
Charge read out timing for VH1X in number of pixels. VH1F VH1R From HREF to leading edge of VH1X. Default is 18Fh. From HREF to trailing edge of VH1X. Default is 1ADh.
Timing Control - VH1X Registers (62h-64h)
62h:
7 VH3F9 r/w 6 VH3F8 r/w 5 VH3F7 r/w 4 VH3F6 r/w 3 VH3F5 r/w 2 VH3F4 r/w 1 VH3F3 r/w 0 VH3F2 r/w
63h:
7 VH3R9 r/w 6 VH3R8 r/w 5 VH3R7 r/w 4 VH3R6 r/w 3 VH3R5 r/w 2 VH3R4 r/w 1 VH3R3 r/w 0 VH3R2 r/w
64h:
7 res r 6 res r 5 res r 4 res r 3 VH3R1 r/w 2 VH3R0 r/w 1 VH3F1 r/w 0 VH3F0 r/w
Charge read out timing for VH3X in number of pixels. VH3F VH3R From HREF to leading edge of VH3X. Default is 1B7h. From HREF to trailing edge of VH3X. Default is 1D5h.
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Black Level Adjust Register (68h)
7 BLK7 r/w 6 BLK6 r/w 5 BLK5 r/w 4 BLK4 r/w 3 BLK3 r/w 2 BLK2 r/w 1 BLK1 r/w 0 BLK0 r/w
BLK
Offset added to input of ADC so that the output of ADC during black pixels is code 64. 00h-FFh represents a voltage range of 0-186mV. Default is 8Fh. This register is automatically updated when black level adjust is enabled.
Version (Minor) Register (69h)
7 7 r 6 6 r 5 5 r 4 4 r 3 3 r 2 2 r 1 1 r 0 0 r
The minor version register in the CS7615 rev A is assigned the value 00h. The Rev B device is assigned the value 01h. With each minor version the value is increased by 1.
Version (Major) Register (6Ah)
7 7 r 6 6 r 5 5 r 4 4 r 3 3 r 2 2 r 1 1 r 0 0 r
The major version register in the CS7615 rev A is assigned the value FFh. With each major version the value is decreased by 1.
Station Address Register (FEh)
7 res r 6 STA6 r/w 5 STA5 r/w 4 STA4 r/w 3 STA3 r/w 2 STA2 r/w 1 STA1 r/w 0 STA0 r/w
STA
CS7615's Station address, 7 MSBs (LSB of complete 8-bit station address determined by read/write bit).
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CS7615
PIN DESCRIPTIONS
CLK2XO
GNDD DO3
VDD DO4
DO5
DO2 DO1
DO0(LSB)
DO6 DO7 DO8 DO9(MSB) CLKO VDD GNDD HSYNC SDA
SCL
44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 CS7615-KQ 6 28 44-pin TQFP 7 27 8 26 Top View 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22
HCLK XTALOUT XTALIN OFDX V2X V1X VH1X V3X VH3X
V4X
VRST INTERP
GNDA
H2 H1
GNDA
FCLKIN RESET GNDA GNDA
VAA FR VAA GNDA AIN
Power Supply Connections VAA - Analog power supply, PIN 19, 21. Nominally +5 volts. VDD - Digital power supply, PIN 5, 41. Nominally +5 volts.
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GNDA - Analog Ground, PIN 12, 15, 16, 18, 22. Analog ground reference. GNDD - Digital Ground, PIN 6, 40. Digital ground reference. Analog Input AIN - Video Input, PIN 17. CCD output signal. Digital Inputs VRST - Vertical sync reset, PIN 10. Used to reset vertical line counter in genlock mode. VRST is falling edge triggered. INTERP - Digital Video Horizontal Data Rate Scaler Enable, PIN 11. Active high logic input sets CLKO output rate to 1x non-interpolated data rate, and the CLK2XO output rate to 2x interpolated data rate (5/2x CLKO rate). Logic low causes the CLKO output rate to be the pixel rate, while CLKX2O is set to twice the pixel rate. FCLKIN - Frequency of crystal input, PIN 13. Logic input identifying the external crystal as a 1x rate or a 2x rate crystal. This pin should be set high for a 1x crystal or clock source; logic low for a 2x crystal or clock source. RESET - Master reset, PIN 14. May be connected to external power-on-reset-circuit. Clears registers to default values. Active logic high. XTALIN - Crystal input, PIN 32. May be 1x or 2x the data rate. XTALOUT - Oscillator output to crystal, PIN 33. If the on-chip oscillator is used, this output connects to the crystal. Timing Generator Outputs HSYNC - Horizontal sync signal, PIN 7. To be used in genlock mode. HSYNC is a rising pulse.
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CS7615
FR- Reset gate clock pulse for CCD, PIN 20. Connect directly to CCD. FR is a rising pulse. H1- Horizontal shift register clock #1, PIN 23. Connect directly to CCD. H2- Horizontal shift register clock #2, PIN 24. Connect directly to CCD. V4X- Vertical shift register clock, PIN 25. Connects to vertical driver. VH3X- Charge read out pulse, PIN 26. Connect to vertical driver. V3X- Vertical shift register clock, PIN 27. Connects to vertical driver. VH1X- Charge read out pulse, PIN 28. Connect to vertical driver. V1X- Vertical shift register clock, PIN 29. Connects to vertical driver. V2X- Vertical shift register clock, PIN 30. Connects to vertical driver. OFDX- Charge sweep out pulse for shutter control, PIN 31. Connect to vertical driver. OFDX is a falling pulse. HCLK- Horizontal line frequency clock, PIN 34. Connect to DC-DC converter. HCLK is a falling pulse when it is in "HREF" output mode. Mosaic Data and clock Outputs DO[0..9] - Digital Mosaic Outputs. CMOS level Mosaic coded CCD output data.
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Pin Name DO0(LSB)
Pin Function
Pin Number
Digital Mosaic Output (LSB) Digital Mosaic Output Digital Mosaic Output Digital Mosaic Output Digital Mosaic Output Digital Mosaic Output Digital Mosaic Output Digital Mosaic Output Digital Mosaic Output Digital Mosaic Output (MSB) Table 6. Digital Mosaic Outputs.
35 36 37 38 42 43 44 1 2 3
DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9(MSB)
CLKO - Mosaic Output Data Clock, PIN 4. Main system output clock, used to strobe outgoing digital CCD mosaic data. on the falling edge.
Data transitions
CLK2XO - Mosaic Output Data Interpolation Clock, PIN 39. Mosaic output data interpolation clock. 2X the CLKO frequency in normal mode (noninterpolated output data... see INTERP description), and 2.5x the CLKO frequency when a 4:5 horizontal data rate scaler is used in the color processor. I2C Serial Control SDA - Primary I2C Data Bus, PIN 8. Primary I2C data bus. Used with SCL to read and write the internal register set. SCL - Primary I2C Clock, PIN 9. Primary I2C Clock. Used with SDA to read and write the internal register set.
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CS7615
PACKAGE DIMENSIONS
44L TQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES DIM A A1 B D D1 E E1 e L MIN 0.000 0.002 0.012 0.478 0.404 0.478 0.404 0.029 0.018 0.000 MAX 0.065 0.006 0.018 0.502 0.412 0.502 0.412 0.037 0.030 7.000 MILLIMETERS MIN MAX 0.00 1.60 0.05 0.15 0.30 0.45 11.70 12.30 9.90 10.10 11.70 12.30 9.90 10.10 0.70 0.90 0.45 0.75 0.00 7.00
JEDEC # : MS-026
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DS231PP6
* Notes *

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